Revert sram split (OpenXiangShan#2518)

* Revert "ICache: split dataArray from 4*128x1024 to 16*128x256 for physical synthesis (OpenXiangShan#2493)"

This reverts commit 787ba0d.

* Revert "bpu: change FTB SRAM width (OpenXiangShan#2497)"

This reverts commit 6955909.

src/main/scala/xiangshan/frontend/FTB.scala

@@ -308,30 +308,18 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
       val update_write_alloc = Input(Bool())
     })
 
+    // Extract holdRead logic to fix bug that update read override predict read result
+    val ftb = Module(new SRAMTemplate(new FTBEntryWithTag, set = numSets, way = numWays, shouldReset = true, holdRead = false, singlePort = true))
+    val ftb_r_entries = ftb.io.r.resp.data.map(_.entry)
 
-    // FTB is FTBEntryWithTag x numWays width, which is 80 x 4 = 320 in KunMingHu
-    // 320 is too large for timing, so use numWays 80-width SRAM instead
-    val ftb = Seq.fill(numWays)(
-      Module(new SRAMTemplate(new FTBEntryWithTag,
-        set = numSets,
-        way = 1,
-        shouldReset = true,
-        holdRead = false, // Extract holdRead logic to fix bug that update read override predict read result
-        singlePort = true)
-      ))
-    val ftb_r_entries = ftb.map(_.io.r.resp.data(0).entry)
-
-    val pred_rdata =
-      HoldUnless(VecInit(ftb.map(_.io.r.resp.data(0))), RegNext(io.req_pc.valid && !io.update_access))
-    ftb.foreach(_.io.r.req.valid := io.req_pc.valid || io.u_req_pc.valid) // io.s0_fire
-    ftb.foreach(
-      _.io.r.req.bits.setIdx := Mux(io.u_req_pc.valid, ftbAddr.getIdx(io.u_req_pc.bits), ftbAddr.getIdx(io.req_pc.bits))
-    ) // s0_idx
+    val pred_rdata   = HoldUnless(ftb.io.r.resp.data, RegNext(io.req_pc.valid && !io.update_access))
+    ftb.io.r.req.valid := io.req_pc.valid || io.u_req_pc.valid // io.s0_fire
+    ftb.io.r.req.bits.setIdx := Mux(io.u_req_pc.valid, ftbAddr.getIdx(io.u_req_pc.bits), ftbAddr.getIdx(io.req_pc.bits)) // s0_idx
 
     assert(!(io.req_pc.valid && io.u_req_pc.valid))
 
-    io.req_pc.ready := ftb.map(_.io.r.req.ready).reduce(_&&_)
-    io.u_req_pc.ready := ftb.map(_.io.r.req.ready).reduce(_&&_)
+    io.req_pc.ready := ftb.io.r.req.ready
+    io.u_req_pc.ready := ftb.io.r.req.ready
 
     val req_tag = RegEnable(ftbAddr.getTag(io.req_pc.bits)(tagSize-1, 0), io.req_pc.valid)
     val req_idx = RegEnable(ftbAddr.getIdx(io.req_pc.bits), io.req_pc.valid)
@@ -347,7 +335,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
     val hit_way = OHToUInt(total_hits)
 
     val u_total_hits = VecInit((0 until numWays).map(b =>
-        ftb(b).io.r.resp.data(0).tag === u_req_tag && ftb(b).io.r.resp.data(0).entry.valid && RegNext(io.update_access)))
+        ftb.io.r.resp.data(b).tag === u_req_tag && ftb.io.r.resp.data(b).entry.valid && RegNext(io.update_access)))
     val u_hit = u_total_hits.reduce(_||_)
     // val hit_way_1h = VecInit(PriorityEncoderOH(total_hits))
     val u_hit_way = OHToUInt(u_total_hits)
@@ -420,17 +408,15 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
       XSPerfAccumulate(f"ftb_hit_way$i", hit && !io.update_access && hit_way === i.U)
     }
 
-    ftb.zipWithIndex.map{
-      case (bank, idx) => bank.io.w.apply(u_valid && u_mask(idx), u_data, u_idx, u_mask(idx))
-    }
+    ftb.io.w.apply(u_valid, u_data, u_idx, u_mask)
 
     // for replacer
     write_set := u_idx
     write_way.valid := u_valid
     write_way.bits := Mux(io.update_write_alloc, allocWriteWay, io.update_write_way)
 
     // print hit entry info
-    Mux1H(total_hits, ftb.map(_.io.r.resp.data(0))).display(true.B)
+    Mux1H(total_hits, ftb.io.r.resp.data).display(true.B)
   } // FTBBank
 
   val ftbBank = Module(new FTBBank(numSets, numWays))

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -90,7 +90,7 @@ trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst wi
 
   def PortNumber = 2
 
-  def partWayNum = 4
+  def partWayNum = 2
   def pWay = nWays/partWayNum
 
   def enableICachePrefetch      = cacheParams.enableICachePrefetch
@@ -711,45 +711,30 @@ class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) e
     val write     = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay)))
   }}
 
-  // Further split the cacheline if necessary
-  val splitNum = 2
-  val wordWidth = gen.getWidth
-  assert(wordWidth % splitNum == 0)
-  val splitedWidth = gen.getWidth / splitNum
+  io.read.req.map(_.ready := !io.write.valid)
 
   val srams = (0 until PortNumber) map { bank =>
-    // Split a cacheline in half for physical synthesis
-    val sramsBanks = (0 until splitNum) map { i =>
-      val sramBank = Module(new SRAMTemplate(
-        UInt(splitedWidth.W),
-        set=nSets/2,
-        way=pWay,
-        shouldReset = true,
-        holdRead = true,
-        singlePort = true
-      ))
-      sramBank.io.r.req.valid := io.read.req(bank).valid
-      sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx)
-      if(bank == 0)
-        sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx && io.write.bits.wmask.asUInt.orR
-      else
-        sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx && io.write.bits.wmask.asUInt.orR
-      sramBank.io.w.req.bits.apply(data=io.write.bits.wdata.asTypeOf(UInt(wordWidth.W))(splitedWidth*(i+1)-1, splitedWidth*i),
-                                   setIdx=io.write.bits.widx,
-                                   waymask=io.write.bits.wmask.asUInt)
-      sramBank
-    }
-    sramsBanks
+    val sramBank = Module(new SRAMTemplate(
+      gen,
+      set=nSets/2,
+      way=pWay,
+      shouldReset = true,
+      holdRead = true,
+      singlePort = true
+    ))
+
+    sramBank.io.r.req.valid := io.read.req(bank).valid
+    sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx)
+
+    if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx
+    else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx
+    sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt)
+
+    sramBank
   }
 
-  val srams_ready = srams.map(sramsBanks => sramsBanks.map(_.io.r.req.ready).reduce(_&&_)).reduce(_&&_)
-  io.read.req.map(_.ready := !io.write.valid && srams_ready)
+  io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_))
+
+  io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen))))
 
-  io.read.resp.rdata := VecInit(srams.map { sramsBanks =>
-    val composeData = sramsBanks.map(_.io.r.resp.asTypeOf(Vec(pWay, UInt(splitedWidth.W))))
-    val data = (0 until pWay).map{i =>
-      (0 until splitNum).map(composeData(_)(i)).reverse.reduce(Cat(_,_))
-    }
-    VecInit(data)
-  })
 }