Core sources and tools for the MIST board

GPL Electronic Design Automation

ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

OpenSoC Fabric - A Network-On-Chip Generator

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

Including the SDK、HDK、Datasheet of RISC-V MCU CH32V307 and other relevant development materials

Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

python library to design chips (Photonics, Analog, Quantum, MEMs, ...), objects for 3D printing or PCBs.

Xilinx Virtual Cable Implementation based on ESP8266

A Tiny Processor Core

A superscalar RISC-V CPU with out-of-order execution and multi-core support

RISC-V Verification Interface

Study notes and tutorial for xilinx hls

A modeling library with virtual components for SystemC and TLM simulators

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Bazel build rules for compiling Verilog

Wavious DDR (WDDR) Physical interface (PHY) Hardware

RISC-V SystemC-TLM simulator

Verilog library for ASIC and FPGA designers

Framework for FPGA-accelerated Middlebox Development

A Chisel RTL generator for network-on-chip interconnects

Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.

RISC-V architecture concurrency model litmus tests

Synthesisable SIMT-style RISC-V GPGPU

Deep learning toolkit-enabled VLSI placement

What if everything is a io_uring?

PCIe (1.0a to 2.0) Virtual host model for verilog

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source