PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g., Verilog, SystemVerilog)

Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operates at RTL to exhaustively examine any machine state left by …

Dactyl-ManuForm, a parameterized ergonomic keyboard translated into Python including a cadquery / Open CASCADE implementation.

implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture

Build userspace NVMe drivers and storage applications with CUDA support

Example for accessing low level RISC-V hardware with C

Mathematical Components compliant Analysis Library

A partial reconfiguration floorplanner for Xilinx FPGAs.

CaDiCaL BackBone Analyzer

Linear-time Temporal Logic guided Greybox Fuzzing (ICSE'22)

Intel x86 bare metal hypervisor for researching snapshot fuzzing ideas.

Companion to the "Introduction to VirtualBox security research" Blog Post

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

An innovative Verilog-A compiler

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

A high-performance, parallel, compilation-based symbolic execution engine

PCIe (1.0a to 2.0) Virtual host model for verilog

What if everything is a io_uring?

Workshop on Open-Source EDA Technology (WOSET)

The lightweight Arch Linux based distro that runs, without root privileges, on top of any other Linux distro.

Deep learning toolkit-enabled VLSI placement

Synthesisable SIMT-style RISC-V GPGPU

Run your GitHub Actions locally 🚀

RISC-V architecture concurrency model litmus tests

Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.

Fast and multi-platform Spotify client with native GUI