fix:fix typo

tkj666 · Jul 18, 2022 · 9bef2c7 · 9bef2c7
1 parent 9b1d7ba
commit 9bef2c7
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Showing 3 changed files with 5 additions and 1 deletion.
diff --git a/src/vsrc/core_types.sv b/src/vsrc/core_types.sv
@@ -146,6 +146,7 @@ package core_types;
         logic dmw0_en;
         logic dmw1_en;
         logic cacop_op_mode_di;
+        logic data_uncache_pre_en;
     } ex_mem_struct;
 
 

diff --git a/src/vsrc/cpu_top.sv b/src/vsrc/cpu_top.sv
@@ -177,7 +177,7 @@ module cpu_top
 
     assign mem_cache_ce = mem_cache_signal[0].ce | mem_cache_signal[1].ce;
     assign mem_cache_we = mem_cache_signal[0].we | mem_cache_signal[1].we;
-    assign mem_uncache_en = mem_cache_signal[0].uncache_en | mem_cache_signal[0].uncache_en;
+    assign mem_uncache_en = mem_cache_signal[0].uncache | mem_cache_signal[0].uncache;
     assign mem_cache_sel =  mem_cache_signal[0].we ? mem_cache_signal[0].sel : mem_cache_signal[1].we ? mem_cache_signal[1].sel : 0;
     assign mem_cache_rd_type = mem_cache_signal[0].ce ? mem_cache_signal[0].rd_type : mem_cache_signal[1].ce ? mem_cache_signal[1].rd_type : 0;
     assign mem_cache_wr_type =  mem_cache_signal[0].ce ? mem_cache_signal[0].wr_type : mem_cache_signal[1].ce ? mem_cache_signal[1].wr_type : 0;

diff --git a/src/vsrc/pipeline/4_mem/mem1.sv b/src/vsrc/pipeline/4_mem/mem1.sv
@@ -73,6 +73,8 @@ module mem1
     logic excp, excp_adem, excp_tlbr, excp_pil, excp_pis, excp_ppi, excp_pme;
     logic [15:0] excp_num;
 
+    logic uncache_en;
+
     assign instr_info = ex_i.instr_info;
     assign special_info = ex_i.instr_info.special_info;
 
@@ -95,6 +97,7 @@ module mem1
         else if (dcache_ack_i) dcache_ack_r <= 1;
     end
 
+    assign uncache_en = ex_i.data_uncache_pre_en || (ex_i.data_addr_trans_en && (tlb_result_i.tlb_mat == 2'b0));
 
     assign access_mem = mem_load_op | mem_store_op;