A small, light weight, RISC CPU soft core
-
Updated
Nov 30, 2024 - Verilog
A small, light weight, RISC CPU soft core
16-bit MIPS Processor from scratch in VHDL
14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.
Add a description, image, and links to the risc-cpu topic page so that developers can more easily learn about it.
To associate your repository with the risc-cpu topic, visit your repo's landing page and select "manage topics."