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Update difftest_api.md
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5265325 committed Sep 1, 2021
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10 changes: 5 additions & 5 deletions doc/difftest_api.md
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```verilog
// 触发异常
`DIFFTEST_MOD_DECL(ArchEvent) (
module DifftestInstrCommit (
input clock, // 时钟
input [ 7:0] coreid, // cpu id,单核时固定为0
input [31:0] intrNO, // 中断号
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);
// 提交指令
`DIFFTEST_MOD_DECL(InstrCommit)(
module DifftestArchIntRegState (
input clock,
input [ 7:0] coreid,
input [ 7:0] index,
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);
// Trap事件,用于告知difftest程序执行结束
`DIFFTEST_MOD_DECL(TrapEvent)(
module DifftestTrapEvent (
input clock,
input [ 7:0] coreid,
input valid, // 执行结束
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);
// 提交CSR寄存器
`DIFFTEST_MOD_DECL(CSRState)(
module DifftestCSRState (
input clock,
input [ 7:0] coreid,
input [ 1:0] priviledgeMode,// 特权模式
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);
// 提交通用寄存器
`DIFFTEST_MOD_DECL(ArchIntRegState)(
module DifftestArchFpRegState (
input clock,
input [ 7:0] coreid,
input [63:0] gpr_0,
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