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  • school_synth_homework_5_fifo Public

    This is my solution of homework #5 of Chip Desing School 2023/2024. The task is located here https://github.com/chipdesignschool/systemverilog-homework.

    SystemVerilog Updated Sep 10, 2024

  • proc_riscv_kass_andra_go Public

    My implementation of RISC-V processor

    SystemVerilog Updated May 16, 2024

  • arduino_tm1638 Public

    C Updated Apr 25, 2024

  • translator_riscv Public

    Translate assembler RISC-V (ISA RV32I) to machine code

    Python Updated Apr 1, 2024

  • school_synth_homework_4 Public

    My solution of homework #4 of chipdesignschool 2023/2024. https://github.com/chipdesignschool/systemverilog-homework

    SystemVerilog Updated Feb 16, 2024