This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

Implementation of Computer Architecture Consepts, Including Multiplier , Control Module, Verilog Elevator, Single cycle processor and mips pipeline with new forwarding unit.

🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021

这是WHU武汉大学2022-2023学年 计卓班 计算机组成与设计 RISC-V CPU 单周期设计，包括Modelsim仿真测试，vivado下FPGA(NEXYS A7)测试。

This repository contains Risc V 32 bit single cycle data path simulated on Logism upon loading instructions.

Singel Cycle Core, RV32-I written in CHISEL (Constructing Hardware In Scala Embedded Language)

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

This repository consists of Load, Store and Read word data paths using a Single Cycle Core.

This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

Repository for Computer Architecture class

A single cycle CPU has been constructed in Verilog.